The proliferation of systems on chips (requiring higher I/O count), increasing process cost per silicon unit area and the need for small form factor chips enabling the computer continuum require finer pitches and smaller packages. At the same time the mobile and ubiquitous segments require low cost solutions. Finer bump pitch generally requires expensive packages due to FLS processing while providing electro-migration capability and reliability of interconnects and package traces. An alternative expensive packaging technology is using an interposer (e.g., silicon or glass interposer) for fine pitch fan out to coarser pitches and LS and using through silicon vias (TSVs) to the package or board interconnects. TSVs, however, tend to add significant cost, limit or degrade power handling and signal integrity and add thickness.